{"id":347,"date":"2015-01-30T10:03:08","date_gmt":"2015-01-30T18:03:08","guid":{"rendered":"http:\/\/www.beyond-circuits.com\/wordpress\/?page_id=347"},"modified":"2016-07-05T14:56:39","modified_gmt":"2016-07-05T22:56:39","slug":"tutorial8","status":"publish","type":"page","link":"https:\/\/www.beyond-circuits.com\/wordpress\/tutorial\/tutorial8\/","title":{"rendered":"Tutorial 8: Stopwatch"},"content":{"rendered":"

In this tutorial, we will build on our counter from the last tutorial to add the ability to start, stop, and reset the time counter. Essentially, we’re going to make a stopwatch.<\/p>\n

Adding the Buttons<\/h1>\n

The ZedBoard has five pushbutton inputs that go to the FPGA. There are two additional pushbuttons, which are for use by the ARM processor that cannot be used by the FPGA fabric. We need to declare the button inputs to the module. We can do this either as five separate inputs or a 5-bit bus. I prefer the bus method.<\/p>\n

Just add the following to the port list:<\/p>\n

input [4:0] btn,<\/code><\/pre>\n
Also, it can be nice to refer to the buttons symbolically as well, so I added the following wire definitions too.<\/p>\n
  wire btnl = btn[0];\r\n  wire btnu = btn[1];\r\n  wire btnr = btn[2];\r\n  wire btnd = btn[3];\r\n  wire btnc = btn[4];\r\n<\/code><\/pre>\n
Of course, we\u00a0need to add the design constraints to declare the IO type and which pin the inputs are connected to. Modify the top.xdc<\/b> file to add the following lines:<\/p>\n
set_property IOSTANDARD LVCMOS25 [get_ports btn]\r\nset_property PACKAGE_PIN P16 [get_ports {btn[4]}]\r\nset_property PACKAGE_PIN R16 [get_ports {btn[3]}]\r\nset_property PACKAGE_PIN R18 [get_ports {btn[2]}]\r\nset_property PACKAGE_PIN T18 [get_ports {btn[1]}]\r\nset_property PACKAGE_PIN N15 [get_ports {btn[0]}]\r\n<\/code><\/pre>\n
Next, we’ll need to look at the buttons. I am going to choose the left button to reset the counter, the center button to stop the counter, and the right button to start the counter. When the button is pressed, the corresponding input value goes high. When the button is released, the button goes low again.<\/p>\n
First, we’ll need some logic to\u00a0detect the rising edge of a button.<\/p>\n
Detecting the Rising Edge<\/h2>\n
\"Tutorial8_sch1\"<\/a>An important thing to note is that the button can be pressed at any time, so it’s impossible to say when the signal will arrive with respect to the clock. This type of signal is referred to as asynchronous<\/em>. It is critically important for your design reliability that you deal with any asynchronous signals by bringing them on chip, then immediately sampling them in a single<\/span> flip-flop. This way, you’ll synchronize the signal to your clock domain. Once we’ve synchronized the button input, we can start looking to see if the button has risen. The schematic will help to illustrate what we are looking for.<\/p>\n
Here is the Verilog code that implements the schematic:<\/p>\n
  reg [1:0] btnl_shift;\r\n  always @(posedge clk)\r\n    btnl_shift <= {btnl_shift,btnl};\r\n  wire btnl_rise = btnl_shift == 2'b01;\r\n<\/code><\/pre>\n
The first line declares a 2-bit register. We then define the register to be set top its value shifted left by one and the button input shifted in. The curly-braces indicate that the values within are to be concatenated together to form a wider bus. So the expression on the right has a width of three bits. This is then assigned back into the 2-bit shift register. This has the effect of setting bit zero of the shift register to the button input and bit one of the shift register to the previous value for bit zero.<\/p>\n
We could code the assignment to btnl_rise<\/em> like this:<\/p>\n
wire btnl_rise = btnl_shift[0] & ~btnl_shift[1];<\/code><\/pre>\n
However,\u00a0I think the comparison to 2’b01 is much cleaner and better indicates to the reader what you’re really looking for.<\/p>\n
Go ahead and add code for the center and right buttons.<\/p>\n
Starting and Stopping the Count<\/h1>\n
To start and stop the counter we just need to start and stop time. The thing that really does that in our design is the counter count<\/em>. It just counts up to ms_limit<\/em>-1, then wraps back to zero. It also generates the millisecond pulse signal ms_pulse<\/em>. To get the counter to stop and start, we create a count_enable<\/em> signal. This will initially be set to zero, and will then go high when btnr_rise<\/em> occurs, and low when btnc_rise<\/em> occurs.<\/p>\n
  reg count_enable = 0;\r\n  always @(posedge clk)\r\n    if (btnr_rise)\r\n      count_enable <= 1;\r\n    else if (btnc_rise)\r\n      count_enable <= 0;\r\n<\/code><\/pre>\n
Now,\u00a0we modify the counter to hold whenever the enable signal is not active. Like this:<\/p>\n
  integer count = 0;\r\n  wire ms_pulse = count == ms_limit-1;\r\n  always @(posedge clk)\r\n    if (count_enable)\r\n      if (ms_pulse)\r\n\tcount <= 0;\r\n      else\r\n\tcount <= count+1;\r\n<\/code><\/pre>\n
Go ahead and build the design and try it out. Can you start and stop the counter? There seems to be a bug. Can you figure out what it is? In case you didn’t actually try the design, the symptom is that you only see one digit displayed when the counter is stopped. Why is that?<\/p>\n
Seeing Both Digits Again<\/h2>\n
If we stop the counter then we also stop the ssdcat<\/em> output which lets us control both digits, causing our bug. What should we do? Simple: use another counter for that function. We could just duplicate the millisecond counter we had before and use that, but I want to try\u00a0something a little more efficient. The exact frequency for the ssdcat<\/em> signal isn’t all that important: it only needs to be above about 60Hz and below 1kHz. Let’s use a counter which naturally wraps, and then not explicitly do a comparison to ms_limit<\/em> to make it wrap early. Then, we’ll just use the most significant bit of the counter for the ssdcat<\/em> output. How many bits should we use? Well, since\u00a0ms_limit<\/em> is 100,000 in the FPGA and we can represent that in 17 bits, a 17-bit counter should work.<\/p>\n
Not so fast there. Remember,\u00a0ms_limit<\/em> is a parameter. In our test bench we set it at\u00a0a much smaller number (100). If we use the real milliseconds in our simulation, which runs at a 1000x faster rate, then our ssdcat<\/em> signal will hardly change at all in the simulation. So we should use our parameter for ms_limit<\/em> in some way for this counter as well. The solution is to just make the counter big enough to count to the next higher power of two after ms_limit<\/em>. Or, in other words, the number of bits for our counter should be the log of ms_limit<\/em>. Here’s the code.<\/p>\n
  reg [0:$clog2(ms_limit)-1] ssdcat_count = 0;\r\n  always @(posedge clk)\r\n    ssdcat_count <= ssdcat_count+1;\r\n  \r\n  initial ssdcat = 0;\r\n  always @(posedge clk)\r\n    ssdcat <= ssdcat_count[0];\r\n<\/code><\/pre>\n
Notice how, in the declaration for ssdcat_count<\/em>, the bit width specification is the reverse of\u00a0what we normally do. A lot of people are confused as to what it means when you do this, but it is actually quite simple. When you specify a width for a bus in Verilog, the number before the colon is the number you are giving to the most significant bit, and the number after the colon is the number you are giving to the least significant bit. In this case, I am specifying that the most significant bit of the counter ssdcat_count<\/em> is zero. This is convenient because later on, I want to assign the most significant bit to ssdcat<\/em>. If I\u00a0do it this way, I can change the size of ssdcat_count<\/em> later, and I won’t have to change the reference to the most significant bit\u2013 it will always be zero, no matter what the width is. Actually, we’re going to need to change the references in the switch<\/b> statement that generates digit<\/em> to use ssdcat_count[0]<\/em> now, instead of ssdcat_pre<\/em> which we have replaced.<\/p>\n
Let’s try the design out again.<\/p>\n
Adding the Clear Button<\/h1>\n
To add the “clear” button, we obviously need to clear our counter. That’s pretty easy:<\/p>\n
  integer count = 0;\r\n  wire ms_pulse = count == ms_limit-1;\r\n  always @(posedge clk)\r\n    if (btnl_rise)\r\n      count <= 0;\r\n    else if (count_enable)\r\n      if (ms_pulse)\r\n\tcount <= 0;\r\n      else\r\n\tcount <= count+1;\r\n<\/code><\/pre>\n
However,\u00a0that doesn’t really do what we want. We’ll also need to clear the BCD digits. Let’s modify our bcd_digit<\/em> module to add a reset signal. Add an input port called reset<\/em>, then add the test for reset<\/em> and clear the digit value when the reset<\/em> input is high. Here is what I have:<\/p>\n
  always @(posedge clk)\r\n    if (reset)\r\n      digit <= 0;\r\n    else if (carry_in)\r\n      if (carry_out)\r\n\tdigit <= 0;\r\n      else\r\n\tdigit <= digit+1;\r\n<\/code><\/pre>\n
Now,\u00a0we just need to pass the btnl_rise signal <\/em><\/em>into the bcd_digit<\/em> module. Let’s do that now. However, did you\u00a0notice how the nine instances of bcd_digit are almost all the same? We can use a Verilog generate<\/b> construct to simplify these instantiations. The generate<\/b> construct allows you to instantiate the bcd_digit<\/em> modules inside a for<\/b> loop. Here’s what it looks like:<\/p>\n
  genvar i;\r\n  generate\r\n    for (i=0; i<num_digits; i=i+1)\r\n      bcd_digit #(10) bcd_digit\r\n\t(\r\n\t .clk(clk),\r\n\t .carry_in(carry[i]),\r\n\t .reset(btnl_rise),\r\n\t .digit(time_digits[i*4+:4]),\r\n\t .carry_out(carry[i+1])\r\n\t );\r\n  endgenerate\r\n<\/code><\/pre>\n
The genvar<\/b> statement declares a variable i<\/em> that we will use in the generate for loop. The generate block is started with the keyword generate<\/b>,\u00a0and concluded with the keyword endgenerate<\/b>. We’ll use a for loop to iterate num_digits<\/em> times, and inside the loop, we instantiate the bcd_digit<\/em> module. Also, note the new syntax for selecting the part of time_digits<\/em> we want the instance to drive. The syntax is vector<\/em>[<\/b>bit<\/em>+:<\/b>width<\/em>]<\/b>. This syntax allows you to dynamically get to a part of a bus. In our case, the bit is given by the expression i*4<\/em>, and the width is 4<\/em>. Why not just use the expression time_digits[i*4+3:i*4],<\/code> you might ask? The answer is a little esoteric. Still, it’s worth explaining. Doing this type of selection only really makes sense when the width of the selection is constant. That is, it can’t change for a given set of parameters or local parameters. The simulator and synthesis tool must be able to figure out what the number is when the design is compiled, and it can’t change after that. The bit selection can be dynamic. By specifying a bit and a width, you allow the compiler to understand whether\u00a0the width is actually static. If you tell it i*4+3 and i*4, then the compiler would have to somehow figure out that (i*4+3)-(i*4) is equal to 3 for all possible values of i<\/em>, so therefore the width must always be 4. It is just too difficult to write a compiler that can figure this out in all possible cases. So, because of this, we have the alternative syntax.<\/p>\n
There are, however, two issues with this code. The first is that we exceed the bounds of the carry signal when i<\/em> has the value 8. We’ll try to drive the carry out, which is unused, into carry[9]<\/em>, which\u00a0doesn’t exist. Before, we had simply left this unconnected. The simplest solution is to just declare carry<\/em> to be one bit wider. So its declaration changes to this:<\/p>\n
  wire [num_digits:0] carry;<\/code><\/pre>\n
That was easy. Here’s our next issue: two of our digits need a parameter value of six, not 10. How do we do that? My solution is to declare a localparam<\/b> value, which indicates which digits should wrap at 10 and which should wrap at six. Now, we can use this parameter inside the for loop. Then we change the instantiation of bcd_digit<\/em> to be a little smarter.<\/p>\n
  localparam wrap_at_six = 9'b001010000;\r\n\r\n  genvar i;\r\n  generate\r\n    for (i=0; i<num_digits; i=i+1)\r\n      bcd_digit #(wrap_at_six[i] ? 6 : 10) bcd_digit\r\n\t(\r\n\t .clk(clk),\r\n\t .carry_in(carry[i]),\r\n\t .reset(btnl_rise),\r\n\t .digit(time_digits[i*4+:4]),\r\n\t .carry_out(carry[i+1])\r\n\t );\r\n  endgenerate<\/code><\/pre>\n
Files<\/h1>\n
Here are the files that I have for this tutorial:<\/p>\n