Inside an FPGA, there may be tens of thousands (or even hundreds of thousands) of flip-flops all running off a single clock. The clock has to arrive at each of those flip-flops at pretty much exactly the same time. By “pretty much exactly”, I mean down-to-the-nanosecond exactly. The FPGA achieves this by using special clock distribution networks within the FPGA. There’s a finite number of these networks\u2013 really, only a handful. So, it’s kind of a big deal to make a signal a clock. In addition, multiple clocks increase the complexity of the static timing analysis which\u00a0needs to occur when synthesizing the device. This can lead to subtle bugs in the design. In short, you really want to minimize the number of clocks in a design.<\/p>\n
But what can we do? The I2S interface uses a clock. Doesn’t that mean we need to use that clock signal? Not really. The sck<\/em> signal is really pretty slow in reality. Normally it is 48 times the audio sample rate, which is, at most, 48KHz. That is 2.3MHz. Maybe in a crazy world where you have 32 bit samples and a 96KHz sample rate you might get it up to the blazing speed of 6.144MHz. Not really all that fast, by FPGA standards.<\/p>\n SCK edge detect circuit<\/p><\/div>\n We can fix this by sampling the sck signal with a much faster FPGA clock. This will be more convenient for us to use. Since sck<\/em> is an asynchronous signal, it is critical that it only go to one flip-flop in our design. If sck<\/em> went to two flip-flops, if it rose at the same time as clk<\/em>, it might get clocked in to one flip-flop but not the other. The circuit shown to the right safely samples the sck<\/em> signal and produces two signals in the clk<\/em> clock domain which pulse whenever sck<\/em> rises or falls.<\/p>\n We can now use those signals as enables to condition the always blocks we had before. In other words, we used to have this always block:<\/p>\n We could now use this one:<\/p>\n As long as our new clock clk<\/em> is more than twice as fast as sck<\/em>, the logic will still work.<\/p>\n Here is the test for this version of the receiver.<\/p>\n In our next<\/a> tutorial, we will add an AXI4 Streaming interface, so we can use our block in the Vivado IP Integrator tool.<\/p>\n","protected":false},"excerpt":{"rendered":" Clocking Until now, we have just been using the sck signal, which is sent by the I2S master. This has kept things simple, but is probably not what we want to do in real life. Inside an FPGA, there may … Continue reading ![\"SCK](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2015\/04\/tutorial18_clk_detect_bd.png\")
<\/a>always @(posedge sck)\r\n wsd <= ws;\r\n<\/code><\/pre>\nalways @(posedge clk)\r\n if (sck_rise) wsd <= ws;\r\n<\/code><\/pre>\nFiles<\/h1>\n
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