Overview<\/h1>\n
To get something basic working, all we need is a module which receives the AXI4 audio stream and delays it, which then produces an AXI4 audio stream out. The block design looks something like this:<\/p>\n
All we do is insert the axi4_stream_delay<\/em> module between the I2S receiver and I2S transmitter. There’s only one gotcha: the axi4_stream_delay<\/em> module doesn’t exist, and we need to write it.<\/p>\n The axi4_stream_delay<\/em> module accepts audio data on an AXI4 streaming slave interface, stores it in a buffer, and then sends it out an AXI4 streaming master interface. To keep things simple, our module will make a few assumptions. The first is that it is receiving audio data so that the packet size is 8 bytes. The second is that we don’t need to keep all the bits in the audio data, we may want to truncate some of the data to save on memory requirements. The third thing is that the maximum delay is fixed as a parameter to the module, but there is a delay input which is able to\u00a0specify how many samples we want to delay. Your module declaration should look something like this. We’ll also be including a scale<\/em> input that\u00a0specifies a scaling value so we can turn up the volume on the audio as it passes though the block.<\/p>\n The DATA_WIDTH<\/em> parameter specifies the width of the TDATA<\/em> bus. The SAMPLE_WIDTH<\/em> parameter specifies the amount of audio data we want to store for each sample. So the module is going to\u00a0only store bits DATA_WIDTH<\/em>-1 through DATA_WIDTH<\/em>–SAMPLE_WIDTH<\/em> in the buffer. The lower bits will be thrown away. Memory space within the FPGA is pretty precious, so it’s a good idea to not waste it. The final parameter MAX_DEPTH<\/em> specifies the maximum amount of delay. To calculate the time of the delay, recall that our audio data is arriving at 48kHz, or one sample every 20.833\u00b5s. The default value of 8192 will produce a maximum delay of 171ms.<\/p>\n Flip-flops in an FPGA are extremely flexible. They can be updated at pretty much any time, and their outputs can be used whenever you want\u00a0by as many consumers as you want. This flexibility comes at a high price, though, in terms of area and power. Sometimes you have a need to store a lot of information and this information doesn’t need to be accessed all the time like a flip-flop. The FPGA contains a large number of small RAM memories. These are much denser than the flip-flops and use much less power. There are limitations about how you can access them, though.<\/p>\n To use a memory in Verilog, you need to declare a reg<\/strong> array. The array will have a width and a depth. Here’s the declaration for the memory in our module:<\/p>\n A circular buffer<\/p><\/div>\n Each element of the array can hold two samples. The array has MAX_DELAY<\/em> elements indexed between 0 and MAX_DELAY<\/em>-1.<\/p>\n In order to use the buffer, we need a pointer which indicates the address that we want to write to and read from in the buffer.<\/p>\n <\/p>\n Here is a declaration for the pointer:<\/p>\n We want our buffer to be circular. That just means that when the pointer has the value of delay<\/em>-1\u00a0and we increment it, it just wraps back to zero. Here is the code to manage ptr<\/em>:<\/p>\n When you code a flip-flop, you are using a Verilog construct which the synthesis tool recognizes as a template for a flip-flop. Likewise, you need to code a memory using a proper memory template which the synthesis tool can then recognize. Also, the memories inside the FPGA are synchronous<\/em>, which means they need to use a clock signal. If you have used SRAM parts before that were asynchronous, these may be a little different. The code below assumes the value being written to the RAM is called in_reg<\/em> and the value being read from the RAM is stored in out_reg<\/em>.<\/p>\n There are a number of different templates for RAMs depending on what type of RAM you want the tool to use. The RAMs used in the FPGA are dual port. Each port can have its own clock, address, write port and read port. For more information on inferring RAMs in your design, consult the Xilinx Answer Record 46515<\/a>.<\/p>\n I have given you the code that reads and writes the circular buffer and the module declaration. You need to provide code which implements an AXI4 slave interface which stores the left and right sample data in in_reg<\/em>, code which takes data in out_reg<\/em> and writes it out the AXI4 streaming master interface, and code which decides when to write and read from the memory.<\/p>\n Since we read and write to the RAM at the same time, the slave and master interfaces need to be synchronized. You enable the RAM when the slave input buffer in_reg<\/em> has valid data in it, and the master interface has sent the data it had in out_reg<\/em>.<\/p>\n When you transfer the data from out_reg to M_AXIS_TDATA you need to align the value such that the MSB of M_AXIS_TDATA is lined up with the MSB of out_reg<\/em>. You will need to shift the out_reg<\/em> value left by DATA_WIDTH<\/em>–SAMPLE_WIDTH<\/em>. We also want to scale the data by the value specified by the scale<\/em> input. To do that, just shift left by\u00a0DATA_WIDTH<\/em>–SAMPLE_WIDTH<\/em>+scale<\/em>.<\/p>\n A test axi4_stream_delay_test.v<\/a> is attached, which can be used to verify your design. This test makes use of the common_test_util and queue modules found in the other tutorials, as well as the AXI4 stream master and slave bus functional models.<\/p>\n Note that the test does not vary the depth<\/em> or scale<\/em> inputs during the test. It is possible to modify those parameters for the test, but in this case, they remain static throughout.<\/p>\n Now build your FPGA using a block design like the one shown above. You should modify the delay parameter on the AXI4 stream delay module to 16384. That gives us about 342ms of delay.<\/p>\n We have to make some changes to the software that initializes the ADAU1761 audio chip. In previous tutorials, we just wanted to receive audio from the line in and send it out to the headphones. In this tutorial, we’ll need to take audio data from the microphone input. Also, I found it helpful to increase the gain on the audio, so we’re going to do that as well.<\/p>\n The changes are that we increase the input gain on the left and write channels. The mixer control registers are at address 0x400a and 0x400c. We write a value of 0xf there to un-mute the microphone input and increase the input gain to 6dB. We also set the left and right mixer gain (0x400b, 0x400d) to 6dB (0x7). Finally we need to turn on the mic bias by setting register 0x4010 to 0x5. Use main.c<\/a> in your SDK project for this tutorial.<\/p>\n Now you just need to find some headphones and a microphone. You want to minimize the sound that a person hears directly when they speak, so over-ear headphones work the best. Alternately,\u00a0you can use ear buds and then over-ear hearing protectors. This is actually the best setup. You’re also going to need a mic. It is important that the mic gain be very high, and you’re really going to want to speak directly into the mic.<\/p>\n It can also be helpful to increase the gain of the audio signal so that the speech is louder in the ear of the speaker. You can do that in the axi4_stream_delay module by scaling the data as it passes through. I found that a factor of eight worked best for my mic and headphones.<\/p>\n Now try it out on your friends, and see what happens.<\/p>\n","protected":false},"excerpt":{"rendered":" In this tutorial, let’s\u00a0have a little fun. Now that we can receive audio data and send it back out, we might as well do something with it. In this tutorial, we’re going to make a speech jammer. What’s a speech … Continue reading ![\"tutorial21_fig1\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2015\/06\/tutorial21_fig1.png\")
<\/a><\/p>\nThe AXI4 stream delay module<\/h1>\n
module axi4_stream_delay #\r\n(\r\nparameter DATA_WIDTH = 32,\r\nparameter SAMPLE_WIDTH = 16,\r\nparameter MAX_DELAY = 8192\r\n)\r\n(\r\ninput ACLK,\r\ninput ARESETN,\r\ninput [$clog2(MAX_DELAY)-1:0] delay,\r\ninput [$clog2(SAMPLE_WIDTH)-1:0] scale,\r\ninput M_AXIS_TREADY,\r\noutput reg M_AXIS_TVALID,\r\noutput reg M_AXIS_TLAST,\r\noutput reg [DATA_WIDTH-1:0] M_AXIS_TDATA,\r\n\r\noutput reg S_AXIS_TREADY,\r\ninput S_AXIS_TVALID,\r\ninput S_AXIS_TLAST,\r\ninput [DATA_WIDTH-1:0] S_AXIS_TDATA\r\n);\r\n<\/pre>\n
The buffer<\/h2>\n
reg [2*SAMPLE_WIDTH-1:0] delay_mem[MAX_DELAY-1:0];<\/pre>\n
![\"A](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2015\/06\/tutorial21_bd1-300x240.png\")
<\/a> reg [$clog2(MAX_DELAY)-1:0] ptr;<\/pre>\n
always @(posedge ACLK)\r\n if (!ARESETN)\r\n ptr <= 0;\r\n else if (buffer enable condition<\/em>)\r\n if (ptr+1 == delay)\r\n\tptr <= 0;\r\n else\r\n\tptr <= ptr+1;\r\n<\/pre>\n
always @(posedge ACLK)\r\n if (!S_AXIS_TREADY && !M_AXIS_TVALID)\r\n begin\r\n\tdelay_mem[ptr] <= in_reg;\r\n\tout_reg <= delay_mem[ptr];\r\n end\r\n<\/pre>\n
Tasks<\/h1>\n
Test<\/h1>\n
Building the FPGA<\/h1>\n
Software<\/h1>\n
Using the speech jammer<\/h1>\n