\/tools\/xilinx<\/code>, so my Vivado install is in \/tools\/xilinx\/Vivado\/2015.4<\/code> and my petalinux install is in \/tools\/xilinx\/petalinux-v2015.4-final<\/code>.<\/p>\nNote that the Petalinux tools only run under Linux, so if you have been using Windows for Vivado, you need to switch to Linux, or you’ll need to adapt these instructions for building on two different machines.<\/p>\n
Building the\u00a0FPGA Design<\/h1>\n
We first need to build an FPGA design to program into the ZYNQ part. Don’t worry if you have not followed along with the previous tutorials. In this tutorial, you will not need to write any Verilog code. Start Vivado\u2013 you may need to source the appropriate settings file to set the environment for your shell. Once Vivado is started click Create New Project.<\/em> This starts the Create New Project Wizard. Click Next<\/em> and enter the project name zedboard_spi<\/em> and then click Next<\/em> again. Click Next<\/em> again to create an RTL project, and then click Next<\/em> again because we don’t need to add any sources. Click Next<\/em>\u00a0once again, since we’re not adding existing IP, and click Next<\/em> because we are adding no constraints. Finally on the Default Part<\/strong> page, click Boards<\/strong> and select the ZedBoard, then click Next<\/em>.<\/p>\n![\"NewProjectBoard\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/NewProjectBoard.png\")
<\/a><\/p>\nFinally, click Finish<\/em> to create the project.<\/p>\nIn the Flow Navigator<\/em> panel, click Create Block Design<\/em> to start a new block design. Name the design system<\/em> and click OK<\/em>. The design will be empty, so click the add IP button to start adding IP. Note that you can mouse over the buttons to see what they are named.\u00a0Select\u00a0the\u00a0ZYNQ7 Processing System and press Enter. This will add the processing system to the FPGA. Click the add IP button again, and add an AXI GPIO block. Add three more AXI GPIO blocks for four total. Click the Regenerate Layout button to organize the diagram.<\/p>\nNow, click the Run Block Automation<\/em> link at the top of the window. This will configure the ARM processors for use on the ZedBoard FPGA board. Click OK. Notice that connections for the DDR memory and FIXED_IO have been added.<\/p>\nNow click the Run Connection Automation<\/em> link. Select the S_AXI connections for each of the four GPIO blocks, then click OK.<\/p>\n![\"GPIO_S_AXI_ConnectionAutomation\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/GPIO_S_AXI_ConnectionAutomation.png\")
<\/a><\/p>\nNow\u00a0click the Regenerate Layout<\/em> button to clean up the diagram. Notice that a Processor Reset System unit and an AXI Interconnect unit were automatically added and connected. This logic allows the ARM processors to talk to the FPGA GPIO units. We’re still going to need to connect the GPIO units to some external pins, however.<\/p>\nWe will connect one GPIO unit to the eight LED outputs, one to the eight switch inputs, one to the five pushbutton inputs, and finally, one to the JA1 Pmod connector, which we will use as a SPI interface.<\/p>\n
Click the Run Connection Automation link again. Notice how the AXI options have gone away but we can still select the GPIO connections. Select the axi_gpio_0 unit to connect to btns_5bits, the axi_gpio_1 to leds_8bits, the axi_gpio_2 to sws_8bits, and the axi_gpio_3 to connect to Custom.<\/p>\n
You should have a diagram that looks something like this:<\/p>\n
![\"T22-Diagram1\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/T22-Diagram1-1024x555.png\")
<\/a><\/p>\nDouble-click on the axi_gpio_0 block. Then select the IP Configuration tab. Notice that the width has been set to 5 bits and the All Inputs box has been checked. The connection automation knew that the buttons were five bits and that they could only be inputs. The leds GPIO has been set to eight outputs, and the switches have been set to eight inputs. Go ahead and click Cancel<\/em>. Double-click on the axi_gpio_3, which is connected to gpio_rtl, and you can see that it is configured for 32 bits and bidirectional operation. Go ahead and set the width to eight, then click OK.<\/p>\nChange the name from gpio_rtl to pmod_a, and change the names of the axi_gpio_0 block to btns_gpio. Likewise, change the other names as well. Your final diagram should look like this:<\/p>\n
![\"T22-FinalDiagram\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/T22-FinalDiagram-1024x559.png\")
<\/a><\/p>\nClick on the Address Editor tab and drill down to the address mapping for the FPGA. It should look like this:<\/p>\n
![\"T22-AddressMap\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/T22-AddressMap.png\")
<\/a><\/p>\nGo back to the Diagram tab and click the Validate Design button. The design should validate successfully.<\/p>\n
Now go ahead and click on the Generate Block Design task in the IP Integrator section of the Flow Navigator (way to the left). The Generate Output Products dialog will pop up. Click the Generate<\/em> button. It may take a few seconds for this dialog to pop up, so be patient. This process builds the RTL code for the block design that you have just entered.<\/p>\nNow, we’ll leave the IP Integrator<\/strong> and select the Project Manager<\/strong>. In the Design Sources section you can see the block diagram that we created. Right clock system<\/em> and select Create HDL Wrapper… This will build the top level of the FPGA design for us. Make sure to let Vivado manage the update.<\/p>\n![\"T22-CreateHDLWrapper\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/T22-CreateHDLWrapper.png\")
<\/a><\/p>\nCreating Constraints<\/h1>\n
The FPGA design itself is almost done. We now need to tell Vivado about the Pmod pins. It already knows about the buttons and LEDs from a board description, but we need to tell Vivado which FPGA pins connect to the Pmod port. From the\u00a0Project Manager section of the Flow Manager, click Add Sources. Select the radio button for Add or create constraints\u00a0<\/strong>and click Next<\/em>. Then click Create File<\/em> and enter the file name system<\/strong>. The file type should be XDC and the location should be local to project. Click OK<\/em>. Then click Finish<\/em> to dismiss the Add Sources<\/em> dialog. If you drill down to the Constraints section of the sources panel, you will see a new constraint file called system.xdc. Double click that file to edit it.<\/p>\nThe constraint file will let us map a pin on the FPGA to a port in the design. This will let us connect that port in the design to a pin on the Pmod connector. We first need the ZedBoard schematic<\/a>. You can see the Pmod connectors on page 3 and the signals are named JA1, JA2, JA3, JA4, JA7, JA8, JA9, JA10 for Pmod connector JA1.<\/p>\n![\"JA1\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/JA1.png\")
<\/a><\/p>\n![\"T22-FPGA-JA1\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2016\/06\/T22-FPGA-JA1.png\")
We now need to find where those signals names are connected to the FPGA. The figure has JA2 highlighted, and you can see that it connected to the FPGA pad AA11.<\/p>\n
All in all we have the following mapping:<\/p>\n
\n\r\nSignal<\/th>\n Pad<\/th>\n<\/tr>\n<\/thead>\n JA1<\/td>\n Y11<\/td>\n<\/tr>\n\r\n JA2<\/td>\n AA11<\/td>\n<\/tr>\n\r\n JA3<\/td>\n Y10<\/td>\n<\/tr>\n\r\n JA4<\/td>\n AA9<\/td>\n<\/tr>\n\r\n JA7<\/td>\n AB11<\/td>\n<\/tr>\n\r\n JA8<\/td>\n AB10<\/td>\n<\/tr>\n\r\n JA9<\/td>\n AB9<\/td>\n<\/tr>\n\r\n JA10<\/td>\n AA8<\/td>\n<\/tr>\n<\/tbody><\/table><\/div>\nset_property PACKAGE_PIN Y11 [get_ports {pmod_a_tri_io[0]}]\r\nset_property PACKAGE_PIN AA11 [get_ports {pmod_a_tri_io[1]}]\r\nset_property PACKAGE_PIN Y10 [get_ports {pmod_a_tri_io[2]}]\r\nset_property PACKAGE_PIN AA9 [get_ports {pmod_a_tri_io[3]}]\r\nset_property PACKAGE_PIN AB11 [get_ports {pmod_a_tri_io[4]}]\r\nset_property PACKAGE_PIN AB10 [get_ports {pmod_a_tri_io[5]}]\r\nset_property PACKAGE_PIN AB9 [get_ports {pmod_a_tri_io[6]}]\r\nset_property PACKAGE_PIN AA8 [get_ports {pmod_a_tri_io[7]}]\r\nset_property IOSTANDARD LVCMOS33 [get_ports pmod_a_tri_io]\r\n<\/pre>\nThe first eight constraints set the package pin for each bit of the pmod_a port. The final constraint sets the IO type on the port to 3.3V CMOS. Note that this can apply to the entire 8 bits of the port. Also note that, for reasons which likely aren’t very good, Vivado has added a suffix of _tri_io to the port name. It doesn’t do this for inputs or outputs, but it feels compelled to do this for bidirectional pins.<\/p>\n
Building the FPGA<\/h1>\n
Save your constraints file and click Generate Bitstream, located in the Program and Debug section of the Flow Navigator. After a few minutes, you should receive a dialog indicating that the build has completed. Elect to open the implemented design.<\/p>\n
Exporting the Design<\/h1>\n
At this point you can go to the File menu and select Export->Export Hardware. In the dialog, make sure Include bitstream is checked, and that you are exporting local to project. This export saves the design and related files in a location where the Software Design Kit (SDK) can find them.<\/p>\n
In the next tutorial<\/a> we build a custom Linux distribution using the FPGA we built in this tutorial.<\/p>\n","protected":false},"excerpt":{"rendered":"In this tutorial, we’re going to take a diversion from the I2S audio and look at embedded Linux. Up until now, we’ve been using bare metal programming for the ARM. This is the easiest method of programming the ARM for … Continue reading