{"id":207,"date":"2014-10-28T21:12:07","date_gmt":"2014-10-29T05:12:07","guid":{"rendered":"http:\/\/www.beyond-circuits.com\/wordpress\/?p=207"},"modified":"2014-10-29T06:23:15","modified_gmt":"2014-10-29T14:23:15","slug":"dual-lifo-2","status":"publish","type":"post","link":"https:\/\/www.beyond-circuits.com\/wordpress\/2014\/10\/dual-lifo-2\/","title":{"rendered":"Dual LIFO"},"content":{"rendered":"\r\n

Table of Contents<\/b><\/p>

1. Interface<\/a><\/span><\/dt>
1.1. Module declaration<\/a><\/span><\/dt>
1.2. Stack ports<\/a><\/span><\/dt>
1.3. Parameters<\/a><\/span><\/dt>
1.4. Definitions<\/a><\/span><\/dt><\/dl><\/dd>
2. Functions<\/a><\/span><\/dt>
3. Logic common to all implementations<\/a><\/span><\/dt>
3.1. Determine read and write signals<\/a><\/span><\/dt>
3.2. Determine count value for stack A<\/a><\/span><\/dt>
3.3. Determine count value for stack B<\/a><\/span><\/dt>
3.4. Generate empty<\/a><\/span><\/dt>
3.5. Generate full<\/a><\/span><\/dt>
3.6. Conditionally generate the full logic<\/a><\/span><\/dt><\/dl><\/dd>
4. BRAM implementation<\/a><\/span><\/dt>
4.1. The data memory<\/a><\/span><\/dt>
4.2. Maintain address pointers<\/a><\/span><\/dt>
4.3. Top-of-stack<\/a><\/span><\/dt>
4.4. Perform memory reads<\/a><\/span><\/dt>
4.5. Perform memory writes<\/a><\/span><\/dt>
4.6. BRAM implementation body<\/a><\/span><\/dt><\/dl><\/dd>
5. Shift register implementation<\/a><\/span><\/dt>
5.1. Shift register implementation of stack A<\/a><\/span><\/dt>
5.2. Shift register implementation of stack B<\/a><\/span><\/dt><\/dl><\/dd>
6. Undefined implementation<\/a><\/span><\/dt>
7. The main module<\/a><\/span><\/dt>
A. Front matter<\/a><\/span><\/dt>
1. Header<\/a><\/span><\/dt>
2. Copyright<\/a><\/span><\/dt><\/dl><\/dd>
B. Downloads<\/a><\/span><\/dt><\/dl><\/div>

\r\n The lifo2<\/code> module implements a dual Last In First\r\n Out stack data structure. The two stack structures share a single\r\n block RAM, or may optionally be constructed from shift registers.\r\n\r\n This module forms the heart of a stack based micro-controller. One\r\n of the stacks is used as a data stack while the other is used as a\r\n subroutine call stack. By implementing these in a single BRAM we\r\n can save a lot of space.\r\n <\/p>

<\/a>1.\u00a0Interface<\/h2><\/div><\/div><\/div>

\r\n The module interface consists of a clock and reset signal, and a\r\n control interface for each stack. \r\n <\/p>

<\/a>1.1.\u00a0Module declaration<\/h3><\/div><\/div><\/div>
<\/a>

\u00a71.1.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>

\r\nmodule lifo2\r\n  \u00a71.3.1. Parameters<\/i><\/a>\r\n  (\r\n   input clk,\r\n   input reset,\r\n   \u00a71.2.1.1. Stack port A<\/i><\/a>,\r\n   \u00a71.2.2.1. Stack port B<\/i><\/a>\r\n   );\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>1.2.\u00a0Stack ports<\/h3><\/div><\/div><\/div>
\r\n\tThe two ports use the suffix a<\/code> and\r\n\tb<\/code> to distinguish interface signals.\r\n\r\n\tA push<\/code><\/em> input indicates that data from the\r\n\tpush_data<\/code><\/em> input should be pushed onto the stack.\r\n\r\n\tA pop<\/code><\/em> input indicates that data should be\r\n\tpopped from the stack. Popped data should be read from the\r\n\ttos<\/code><\/em> output during the same cycle that\r\n\tpop<\/code><\/em> is valid.\r\n\r\n\tIt is completely normal to push and pop data on the same clock\r\n\tcycle.\r\n      <\/p>
\r\n\tStatus signals empty<\/code><\/em> and\r\n\tfull<\/code><\/em> indicate if the stack is empty or full.\r\n\r\n\tThe count<\/code><\/em> output provides the number of valid\r\n\tentries currently on the stack.\r\n      <\/p>
<\/a>1.2.1.\u00a0Stack port A<\/h4><\/div><\/div><\/div>
<\/a>
\u00a71.2.1.1<\/b>: \u00a71.1.1<\/a><\/p><\/td><\/tr>
\r\n   input push_a,\r\n   input pop_a,\r\n   output reg empty_a,\r\n   output reg full_a,\r\n   output reg `CNT_T count_a,\r\n   output `DATA_T tos_a,\r\n   input `DATA_T push_data_a\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>1.2.2.\u00a0Stack port B<\/h4><\/div><\/div><\/div>
<\/a>
\u00a71.2.2.1<\/b>: \u00a71.1.1<\/a><\/p><\/td><\/tr>
\r\n   input push_b,\r\n   input pop_b,\r\n   output reg empty_b,\r\n   output reg full_b,\r\n   output reg `CNT_T count_b,\r\n   output `DATA_T tos_b,\r\n   input `DATA_T push_data_b\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>1.3.\u00a0Parameters<\/h3><\/div><\/div><\/div>
\r\n\tA depth<\/code><\/em> parameter specifies the depth\r\n\tfor each of the stacks. \r\n\r\n\tFor the BRAM implementation, the size of the RAM is just the\r\n\tsum of the two depth<\/code><\/em> parameters.\r\n\r\n\tFor the shift register implementation each stack uses its\r\n\tdepth<\/code><\/em> parameter independently.\r\n\r\n\tThe width<\/code><\/em> parameter specifies the data\r\n\twidth. This is the same for both stacks.\r\n      <\/p>
\r\n\tThe implementation<\/code><\/em> parameter may be set\r\n\tto \"BRAM\"<\/code> or \"SRL\"<\/code> to\r\n\tselect between BRAM and shift register implementations. Note\r\n\tthat the quotes are required.\r\n      <\/p>
\r\n\tThe full_checking<\/code><\/em> specifies whether the\r\n\tlogic that generates the full<\/code><\/em> outputs should\r\n\tbe generated.\r\n\r\n\tIn the case of the shift register implementation the concept\r\n\tof full is easy to implement and sensible. With this\r\n\timplementation, there really are two independent stacks.\r\n\r\n\tHowever, with the BRAM implementation the concept of full is a\r\n\tlittle harder to pin down. Is the stack full when the number\r\n\tof elements is equal to its depth<\/code><\/em>\r\n\tparameter? This seems overly restrictive since there may still\r\n\tbe plenty of room for it to grow. But if it does grow then it\r\n\tdoes so at the expense of the other stack.\r\n\r\n\tThere is a further difficulty if both stacks are almost\r\n\tfull. If you push to both stacks then you will overflow one of\r\n\tthe stacks. Which one? The one that is already over its posted\r\n\tlimit? The logic to implement this seems needlessly complex.\r\n\r\n\tSo the compromise here is to implement the strict full\r\n\tchecking for the BRAM implementation when the\r\n\tfull_checking<\/code><\/em> parameter is true and to\r\n\tnot generate any full checking logic at all if it is false.\r\n      <\/p>
<\/a>
\u00a71.3.1<\/b>: \u00a71.1.1<\/a><\/p><\/td><\/tr>
\r\n  #(\r\n    parameter depth_a = 512,\r\n    parameter depth_b = 512,\r\n    parameter width = 32,\r\n    parameter implementation = \"SRL\",\r\n    parameter full_checking = 0,\r\n    parameter depth = depth_a+depth_b\r\n    )\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>1.4.\u00a0Definitions<\/h3><\/div><\/div><\/div>
\r\n\tHere are some definitions that we can make use of\r\n\tlater. DATA_T<\/code> is used for data\r\n\tvalues. PTR_T<\/code> is used for pointers like the\r\n\ttop of stack pointer. The CNT_T<\/code> definition\r\n\tis suitable for holding a count. Note that this value needs to\r\n\thold a value of 0 as well as a value of\r\n\tdepth<\/code><\/em> so it may be larger than the\r\n\tPTR_T<\/code> value.\r\n      <\/p>
<\/a>
\u00a71.4.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n`define DATA_T [width-1:0]\r\n`define PTR_T [log2(depth)-1:0]\r\n`define CNT_T [log2(depth+1)-1:0]\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>2.\u00a0Functions<\/h2><\/div><\/div><\/div>
\r\n      The log2<\/code> function computes the log base 2\r\n      of its input value. This function is used to computer widths of\r\n      pointer and count values.\r\n    <\/p>
<\/a>
\u00a72.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n   function integer log2;\r\n      input [31:0] value;\r\n      begin\r\n\t value = value-1;\r\n\t for (log2=0; value>0; log2=log2+1)\r\n\t   value = value>>1;\r\n      end\r\n   endfunction\r\n    <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.\u00a0Logic common to all implementations<\/h2><\/div><\/div><\/div>
<\/a>3.1.\u00a0Determine read and write signals<\/h3><\/div><\/div><\/div>
\r\n\tThe writing<\/code><\/em> signals indicate that we are\r\n\twriting to the corresponding stack. This occurs when the push\r\n\tsignal is asserted and there is space on the stack or if the\r\n\tpush signal is asserted and a pop is asserted as well. In this\r\n\tcase we can perform the operation even though the stack is\r\n\tfull.\r\n      <\/p>
\r\n\tThe reading<\/code><\/em> signal indicates that\r\n\twe are reading from the corresponding stack. It is just the\r\n\tpop signal qualified with not empty.\r\n      <\/p>
<\/a>
\u00a73.1.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  wire writing_a = push_a && (!full_a || pop_a);\r\n  wire writing_b = push_b && (!full_b || pop_b);\r\n  wire reading_a = pop_a && !empty_a;\r\n  wire reading_b = pop_b && ! empty_b;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.2.\u00a0Determine count value for stack A<\/h3><\/div><\/div><\/div>
\r\n\tWe first generate the next_count_a<\/code><\/em>\r\n\tvalue. Incrementing if we are writing but not reading,\r\n\tdecrementing if we are reading and not writing and leaving the\r\n\tcount the same if we are both reading and writing or neither\r\n\treading or writing.\r\n\r\n\tWe use a separate combinational always block to generate a\r\n\tnext value signal next_count_a<\/code><\/em>. This signal\r\n\tis used by later code to determine empty and full conditions.\r\n      <\/p>
<\/a>
\u00a73.2.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  reg `CNT_T next_count_a;\r\n  always @(*)\r\n    if (writing_a && !reading_a)\r\n      next_count_a = count_a + 1;\r\n    else if (reading_a && !writing_a)\r\n      next_count_a = count_a - 1;\r\n    else\r\n      next_count_a = count_a;\r\n\r\n  always @(posedge clk)\r\n    if (reset)\r\n      count_a <= 0;\r\n    else\r\n      count_a <= next_count_a;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.3.\u00a0Determine count value for stack B<\/h3><\/div><\/div><\/div>
\r\n\tHere we generate the count values for stack B.\r\n      <\/p>
<\/a>
\u00a73.3.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  reg `CNT_T next_count_b;\r\n  always @(*)\r\n    if (writing_b && !reading_b)\r\n      next_count_b = count_b + 1;\r\n    else if (reading_b && !writing_b)\r\n      next_count_b = count_b - 1;\r\n    else\r\n      next_count_b = count_b;\r\n  \r\n  always @(posedge clk)\r\n    if (reset)\r\n      count_a <= 0;\r\n    else\r\n      count_b <= next_count_b;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.4.\u00a0Generate empty<\/h3><\/div><\/div><\/div>
\r\n\tHere we generate the logic for determining if either stack is\r\n\tempty. The stack is empty if on the next clock its count will\r\n\tbe zero.\r\n      <\/p>
<\/a>
\u00a73.4.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  always @(posedge clk)\r\n    if (reset)\r\n      empty_a <= 1;\r\n    else\r\n      empty_a <= next_count_a == 0;\r\n\r\n  always @(posedge clk)\r\n    if (reset)\r\n      empty_b <= 1;\r\n    else\r\n      empty_b <= next_count_b == 0;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.5.\u00a0Generate full<\/h3><\/div><\/div><\/div>
\r\n\tFull is pretty simple as well. We go full when the next count\r\n\tvalue will be equal to the depth<\/code><\/em>\r\n\tparameter of the stack. Writes will not occur when the stack\r\n\tis full so there can never be a case when the next count value\r\n\tis greater than the depth.\r\n      <\/p>
<\/a>
\u00a73.5.1<\/b>: \u00a73.6.1<\/a><\/p><\/td><\/tr>
\r\n  always @(posedge clk)\r\n    if (reset)\r\n      full_a <= 0;\r\n    else\r\n      full_a <= next_count_a == depth_a;\r\n\r\n  always @(posedge clk)\r\n    if (reset)\r\n      full_b <= 0;\r\n    else\r\n      full_b <= next_count_b == depth_b;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>3.6.\u00a0Conditionally generate the full logic<\/h3><\/div><\/div><\/div>
\r\n\tAs discussed in Section\u00a01.3, “Parameters”<\/a>, based on\r\n\tthe value of the full_checking<\/code><\/em>\r\n\tparameter we either create the checking logic or just stub the\r\n\tfull signals out to always false.\r\n      <\/p>
<\/a>
\u00a73.6.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  generate\r\n    if (full_checking)\r\n      begin\r\n        \u00a73.5.1. Generate full<\/i><\/a>\r\n      end\r\n    else\r\n      begin\r\n\tinitial full_a = 0;\r\n\tinitial full_b = 0;\r\n      end\r\n  endgenerate\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>4.\u00a0BRAM implementation<\/h2><\/div><\/div><\/div>
\r\n      This section describes the BRAM implementation of the dual LIFO.\r\n    <\/p>
<\/a>4.1.\u00a0The data memory<\/h3><\/div><\/div><\/div>
<\/a>
\u00a74.1.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  reg `DATA_T mem [depth-1:0];\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>4.2.\u00a0Maintain address pointers<\/h3><\/div><\/div><\/div>
<\/a>
Figure\u00a01.\u00a0The pointer to the top of the A stack grows down while\r\n\tthe pointer to the top of the B stack grows up<\/b><\/p>
<\/object><\/div><\/div><\/div>
\r\n\tHere we maintain the address pointers into the RAM. The\r\n\tpointer for stack A starts at address zero and works up, while\r\n\tthe pointer for stack B starts at the last address and works\r\n\tdown.\r\n      <\/p>
<\/a>
\u00a74.2.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  wire `PTR_T ptr_a = writing_a ? count_a `PTR_T : (count_a `PTR_T)-1;\r\n  wire `PTR_T ptr_b = (depth-1)-(writing_b ? count_b `PTR_T\r\n                                           : (count_b `PTR_T)-1);\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>4.3.\u00a0Top-of-stack<\/h3><\/div><\/div><\/div>
\r\n\tOne limitation of the BRAM implementation is that we only have\r\n\ttwo ports. One port must be used for each stack since both\r\n\tstacks can operate simultaneously.\r\n\r\n\tThe solution to this problem is to recognize that if we are\r\n\tboth pushing and popping the stack then we are really only\r\n\toperating on the top element. This element can be stored in a\r\n\tregister and no actual memory operation needs to occur.\r\n      <\/p>
<\/a>4.3.1.\u00a0Top-of-stack shadow registers<\/h4><\/div><\/div><\/div>
\r\n\t  The tos_shadow<\/code><\/em> registers hold the latest\r\n\t  value pushed onto the stack.\r\n\t<\/p>
<\/a>
\u00a74.3.1.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  reg `DATA_T tos_shadow_a;\r\n  always @(posedge clk)\r\n    if (reset)\r\n      tos_shadow_a <= 0;\r\n    else if (writing_a)\r\n      tos_shadow_a <= push_data_a;\r\n\r\n  reg `DATA_T tos_shadow_b;\r\n  always @(posedge clk)\r\n    if (reset)\r\n      tos_shadow_b <= 0;\r\n    else if (writing_b)\r\n      tos_shadow_b <= push_data_b;\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>4.3.2.\u00a0Select between top-of-stack shadow registers and memory read values<\/h4><\/div><\/div><\/div>
\r\n\t  Here we determine if we should use the memory read value or\r\n\t  the top-of-stack shadow register to provide the top-of-stack\r\n\t  value.\r\n\r\n\t  If we are popping the stack then the new top-of-stack value\r\n\t  should come from the memory read. Otherwise we should just\r\n\t  use the value in the top-of-stack shadow register.\r\n\t<\/p>
<\/a>
\u00a74.3.2.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  reg use_mem_rd_a;\r\n  always @(posedge clk)\r\n    if (reset)\r\n      use_mem_rd_a <= 0;\r\n    else if (writing_a)\r\n      use_mem_rd_a <= 0;\r\n    else if (reading_a)\r\n      use_mem_rd_a <= 1;\r\n\r\n  reg use_mem_rd_b;\r\n  always @(posedge clk)\r\n    if (reset)\r\n      use_mem_rd_b <= 0;\r\n    else if (writing_b)\r\n      use_mem_rd_b <= 0;\r\n    else if (reading_b)\r\n      use_mem_rd_b <= 1;\r\n\r\n  assign tos_a = use_mem_rd_a ? mem_rd_a : tos_shadow_a;\r\n\r\n  assign tos_b = use_mem_rd_b ? mem_rd_b : tos_shadow_b;\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>4.4.\u00a0Perform memory reads<\/h3><\/div><\/div><\/div>
\r\n\tHere we read from the stack. The values read will be the\r\n\ttop-of-stack outputs if we are reading from the stack but not\r\n\twriting to it.\r\n      <\/p>
<\/a>
\u00a74.4.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  reg `DATA_T mem_rd_a;\r\n  always @(posedge clk)\r\n    if (reading_a)\r\n      mem_rd_a <= mem[ptr_a];\r\n\r\n  reg `DATA_T mem_rd_b;\r\n  always @(posedge clk)\r\n    if (reading_b)\r\n      mem_rd_b <= mem[ptr_b];\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>4.5.\u00a0Perform memory writes<\/h3><\/div><\/div><\/div>
\r\n\tConversely if we are writing to the stack but not reading then\r\n\twe perform a memory write.\r\n      <\/p>
<\/a>
\u00a74.5.1<\/b>: \u00a74.6.1<\/a><\/p><\/td><\/tr>
\r\n  always @(posedge clk)\r\n    if (writing_a && !reading_a)\r\n      mem[ptr_a] <= tos_a;\r\n\r\n  always @(posedge clk)\r\n    if (writing_b && !reading_b)\r\n      mem[ptr_b] <= tos_b;\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>4.6.\u00a0BRAM implementation body<\/h3><\/div><\/div><\/div>
\r\n\tHere we collect all the components of the BRAM implementation.\r\n      <\/p>
<\/a>
\u00a74.6.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  \u00a74.1.1. The data memory<\/i><\/a>\r\n  \u00a74.2.1. Maintain address pointers<\/i><\/a>\r\n  \u00a74.4.1. Perform memory reads<\/i><\/a>\r\n  \u00a74.5.1. Perform memory writes<\/i><\/a>\r\n  \u00a74.3.1.1. Top-of-stack shadow registers<\/i><\/a>\r\n  \u00a74.3.2.1. Select between top-of-stack shadow registers and memory read values<\/i><\/a>\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>5.\u00a0Shift register implementation<\/h2><\/div><\/div><\/div>
<\/a>5.1.\u00a0Shift register implementation of stack A<\/h3><\/div><\/div><\/div>
\r\n\tThere may be situations where two stacks are needed but we\r\n\tdon't want to use a block RAM, or if both stacks don't need to\r\n\tbe very large and we want to save the overhead of the RAM\r\n\timplementation. This alternate shift register implementation\r\n\tmay be used instead.\r\n      <\/p>
\r\n\tThe basic idea of the shift register implementation is to use\r\n\ta shift register for each bit of the data word. We then\r\n\tconcatenate the head of the shift registers together to form\r\n\tthe top of the stack.\r\n      <\/p>
<\/a>5.1.1.\u00a0Pop data off the shift register<\/h4><\/div><\/div><\/div>
\r\n\t  Here we shift the register left, shifting in a zero value.\r\n\t<\/p>
<\/a>
\u00a75.1.1.1<\/b>: \u00a75.1.1<\/a><\/p><\/td><\/tr>
\r\nsrl <= {srl[depth-2:0],1'b0}\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>5.1.2.\u00a0Push data onto the shift register<\/h4><\/div><\/div><\/div>
\r\n\t  Here we shift the push data onto the shift register. This\r\n\t  will only happen when the shift register is not full.\r\n\t<\/p>
<\/a>
\u00a75.1.2.1<\/b>: \u00a75.1.1<\/a><\/p><\/td><\/tr>
\r\nsrl <= {push_data_a[i],srl[depth_a-1:1]}\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>5.1.3.\u00a0Swap data at the top of the shift register<\/h4><\/div><\/div><\/div>
\r\n\t  Here we just replace the leftmost value in the shift\r\n\t  register with the new pushed value.\r\n\t<\/p>
<\/a>
\u00a75.1.3.1<\/b>: \u00a75.1.1<\/a><\/p><\/td><\/tr>
\r\nsrl <= {push_data_a[i],srl[depth_a-2:0]}\r\n\t<\/pre><\/td><\/tr><\/table><\/div><\/div>
\r\n\tWe use a generate for loop to implement each shift register\r\n\tand a case statement to update it based on the push and pop\r\n\tconditions.\r\n      <\/p>
<\/a>
\u00a75.1.1<\/b>: \u00a75.1<\/a><\/p><\/td><\/tr>
\r\nfor (i=0; i<width; i=i+1)\r\n  begin : srl_a\r\n    reg [depth_a-1:0] srl;\r\n    always @(posedge clk)\r\n      case ({writing_a,reading_a})\r\n\t2'b01: \u00a75.1.1.1. Pop data off the shift register<\/i><\/a>;\r\n\t2'b10: \u00a75.1.2.1. Push data onto the shift register<\/i><\/a>;\r\n\t2'b11: \u00a75.1.3.1. Swap data at the top of the shift register<\/i><\/a>;\r\n      endcase\r\n\r\n      assign tos_a[i] = srl[depth_a-1];\r\n  end\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>5.2.\u00a0Shift register implementation of stack B<\/h3><\/div><\/div><\/div>
\r\n\tThe implementation for stack B is the same as for stack A but\r\n\twith the appropriate name changes.\r\n      <\/p>
<\/a>
\u00a75.2.1<\/b>: \u00a75.1<\/a><\/p><\/td><\/tr>
\r\nfor (i=0; i<width; i=i+1)\r\n  begin : srl_b\r\n    reg [depth_b-1:0] srl;\r\n    always @(posedge clk)\r\n      case ({writing_b,reading_b})\r\n\t2'b01: srl <= {srl[depth_b-2:0],1'b0};\r\n\t2'b10: srl <= {push_data_b[i],srl[depth_b-1:1]};\r\n\t2'b11: srl <= {push_data_b[i],srl[depth_b-2:0]};\r\n      endcase\r\n      assign tos_b[i] = srl[depth_b-1];\r\n  end\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
\r\n      For the shift register implementation we just declare the\r\n      generate loop variable and then instantiate the two stacks.\r\n    <\/p>
<\/a>
\u00a75.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n  genvar i;\r\n  \u00a75.1.1. Shift register implementation of stack A<\/i><\/a>\r\n  \u00a75.2.1. Shift register implementation of stack B<\/i><\/a>\r\n    <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>6.\u00a0Undefined implementation<\/h2><\/div><\/div><\/div>
<\/a>
\u00a76.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n\tinitial\r\n\t  begin\r\n\t    $display(\"***ERROR: %m: Undefined implementation \\\"%0s\\\".\",implementation);\r\n\t    $finish;\r\n\t  end\r\n    <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>7.\u00a0The main module<\/h2><\/div><\/div><\/div>
\r\n      This is where we tie everything together.\r\n    <\/p>
<\/a>
\u00a77.1<\/b><\/p><\/td><\/tr>
\r\n\u00a71.1. Header<\/i><\/a>\r\n\u00a72.1. Copyright<\/i><\/a>\r\n\r\n`timescale 1ns\/1ns\r\n\u00a71.4.1. Definitions<\/i><\/a>\r\n\r\n\u00a71.1.1. Module declaration<\/i><\/a>\r\n\r\n\u00a72.1. Functions<\/i><\/a>\r\n\r\n\u00a73.1.1. Determine read and write signals<\/i><\/a>\r\n\r\n\u00a73.2.1. Determine count value for stack A<\/i><\/a>\r\n\u00a73.3.1. Determine count value for stack B<\/i><\/a>\r\n\r\n\u00a73.4.1. Generate empty<\/i><\/a>\r\n\u00a73.6.1. Conditionally generate the full logic<\/i><\/a>\r\n\r\n`ifndef SYNTHESIS\r\n   initial\r\n     $display(\"***INFO: %m: lifo2.v implementation=\\\"%0s\\\".\",implementation);\r\n`endif\r\n  generate\r\n    if (implementation == \"BRAM\")\r\n      begin : bram_implementation\r\n        \u00a74.6.1. BRAM implementation body<\/i><\/a>\r\n      end\r\n    else if (implementation == \"SRL\")\r\n      begin : srl_implementation\r\n        \u00a75.1. Shift register implementation<\/i><\/a>\r\n      end\r\n    else\r\n      begin\r\n        \u00a76.1. Undefined implementation<\/i><\/a>\r\n      end\r\n  endgenerate\r\nendmodule\r\n    <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>A.\u00a0Front matter<\/h2>
<\/a>1.\u00a0Header<\/h3><\/div><\/div><\/div>
<\/a>
\u00a71.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n\/\/-----------------------------------------------------------------------------\r\n\/\/ Title         : Dual LIFO stack\r\n\/\/ Project       : Common\r\n\/\/-----------------------------------------------------------------------------\r\n\/\/ File          : lifo2.v\r\n\/\/-----------------------------------------------------------------------------\r\n\/\/ Description :\r\n\/\/ \r\n\/\/ Two Synchronous LIFO stacks using a single BRAM.\r\n\/\/\r\n\/\/ The stacks start at each end and grow to the middle.\r\n\/\/\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div>
<\/a>2.\u00a0Copyright<\/h3><\/div><\/div><\/div>
<\/a>
\u00a72.1<\/b>: \u00a77.1<\/a><\/p><\/td><\/tr>
\r\n\/\/-----------------------------------------------------------------------------\r\n\/\/ Copyright 2009 Beyond Circuits. All rights reserved.\r\n\/\/\r\n\/\/ Redistribution and use in source and binary forms, with or without modification,\r\n\/\/ are permitted provided that the following conditions are met:\r\n\/\/   1. Redistributions of source code must retain the above copyright notice, \r\n\/\/      this list of conditions and the following disclaimer.\r\n\/\/   2. Redistributions in binary form must reproduce the above copyright notice, \r\n\/\/      this list of conditions and the following disclaimer in the documentation \r\n\/\/      and\/or other materials provided with the distribution.\r\n\/\/\r\n\/\/ THIS SOFTWARE IS PROVIDED BY THE BEYOND CIRCUITS ``AS IS'' AND ANY EXPRESS OR \r\n\/\/ IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \r\n\/\/ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT \r\n\/\/ SHALL BEYOND CIRCUITS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r\n\/\/ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT\r\n\/\/ OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \r\n\/\/ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \r\n\/\/ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY \r\n\/\/ OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n\/\/------------------------------------------------------------------------------\r\n      <\/pre><\/td><\/tr><\/table><\/div><\/div><\/div>
<\/a>B.\u00a0Downloads<\/h2>
\r\n      The Verilog code for lifo2.v<\/code> can be\r\n      downloaded here<\/a>. Since\r\n      this post is so long I have also included a link the article in\r\n      PDF form here<\/a>.\r\n    <\/p><\/div><\/div>\r\n\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6,3,4],"tags":[],"class_list":["post-207","post","type-post","status-publish","format-standard","hentry","category-fpga","category-hdl","category-verilog"],"_links":{"self":[{"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/posts\/207","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/comments?post=207"}],"version-history":[{"count":10,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/posts\/207\/revisions"}],"predecessor-version":[{"id":218,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/posts\/207\/revisions\/218"}],"wp:attachment":[{"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/media?parent=207"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/categories?post=207"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.beyond-circuits.com\/wordpress\/wp-json\/wp\/v2\/tags?post=207"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}