This will put in an IP Packager project. Edit the top level file myip_v1_0<\/em>. I’m using Verilog but it works the same for VHDL. Instantiate a new dummy module at the bottom of the file:<\/p>\n Now, we would like to create the new module. So we go to File\u2192Add Sources\u2026<\/em> and create the new source file. Select Add or create design sources<\/em> and click Next<\/em><\/strong>. Click Create File\u00a0\u2026<\/strong><\/em>, type the file name dummy<\/em> and click OK<\/em><\/strong>. Click Finish<\/em><\/strong>. When the Define Module<\/strong> dialog pops up, just click OK<\/em><\/strong>. Click Yes<\/em><\/strong> to the dialog saying you haven’t changed anything. You now have a file defined for your dummy<\/em> module.<\/p>\n Now click on the Merge changes from File Groups Wizard<\/span> link. You will then get a link saying 2 warnings<\/span>. Click on that, and you will see two warnings about your dummy.v<\/em> file being on a path which is not relative to your IP root directory. What has happened is that Vivado placed the new file outside the IP component. If you go ahead and package your IP, you cannot use the packaged IP because it will be missing this file. Seems like a Vivado (2014.4) bug to me.<\/p>\n So how should we fix this? I don’t know how to move files in Vivado, but we can create the file in a different location when we make the new file. To do that, first delete the dummy file and remove it from disk. Just select the file, then right-click and select Remove File from Project<\/em>. Select the checkbox to also delete it from disk and click OK<\/em><\/strong>.<\/p>\n When you merge your changes in the File Groups<\/strong> step, you should not get any warnings. You can then package your IP and use it in your designs.<\/p>\n Hopefully this will be fixed in the next release of Vivado.<\/p>\n","protected":false},"excerpt":{"rendered":" Vivado has the ability to create and manage your own IP, which is a good thing. But there are some real gotchas when doing something like this, the first being that it doesn’t seem to place HDL files in the … Continue reading \/\/ Add user logic here\r\ndummy dummy (.clk(s00_axi_aclk));\r\n\/\/ User logic ends\r\n<\/pre>\n
![\"files_fig1\"](\"https:\/\/www.beyond-circuits.com\/wordpress\/wp-content\/uploads\/2015\/03\/files_fig1.png\")
<\/a>Save the file and look at the design sources. You will see that there is now a new undefined module in the design called dummy<\/em>. It should look like the figure to the right:<\/p>\n<\/a>Ready to package that IP? Go to the Package IP<\/strong> tab in the Project Manager<\/strong> window. Then, select File Groups<\/strong> in the Packaging Steps <\/strong>window. You should see a window like the figure on the right.<\/p>\n<\/a>Now go to Add Sources again, and after clicking Create File\u2026<\/em>, specify the file name dummy.v<\/em>, then select a new file location. <\/a>Navigate to your ip_repo<\/em> area and into myip_1_0. <\/em>Select the hdl<\/em> directory, and click Select<\/em><\/strong>. Then click OK<\/em><\/strong> and then Finish<\/em><\/strong> to create the file. This will place the file in the proper location in the IP repository.<\/p>\n