{"id":900,"date":"2016-03-10T13:49:53","date_gmt":"2016-03-10T21:49:53","guid":{"rendered":"http:\/\/www.beyond-circuits.com\/wordpress\/?p=900"},"modified":"2016-10-31T13:39:11","modified_gmt":"2016-10-31T21:39:11","slug":"detecting-the-rising-edge-of-a-short-pulse","status":"publish","type":"post","link":"https:\/\/www.beyond-circuits.com\/wordpress\/2016\/03\/detecting-the-rising-edge-of-a-short-pulse\/","title":{"rendered":"Detecting the rising edge of a short pulse"},"content":{"rendered":"

A reader is going through my ZedBoard tutorial and had some questions about detecting the rising edge of a pulse. The tutorial<\/a> in question is using a ZedBoard to make a stopwatch. Kind of overkill in terms of hardware, but you have to start somewhere when you’re\u00a0learning to code.<\/p>\n

TRAN MINHHAI’s question asked: what do you do when the rising edge might just be a pulse, and the pulse might last less than a single clock cycle? The answer is to use a flip-flop with the input signal going to an asynchronous set input. The data input is just zero, and the clock signal is the one we are synchronizing to.<\/p>\n

Here is the code:<\/p>\n

\r\n`timescale 1ns\/1ns\r\nmodule edge_detect\r\n  (\r\n   input clk,\r\n   input btnl,\r\n   output btnl_rise\r\n   );\r\n\r\n  reg btnl_held = 0;\r\n  always @(posedge clk or posedge btnl)\r\n    if (btnl)\r\n      btnl_held <= 1;\r\n    else\r\n      btnl_held <= 0;\r\n\r\n  reg [1:0] btnl_shift = 0;\r\n  always @(posedge clk)\r\n    btnl_shift <= {btnl_shift,btnl_held};\r\n  \r\n  assign btnl_rise = btnl_shift == 2'b01;\r\nendmodule\r\n<\/code><\/pre>\n
I also wrote a little test to go with it. Notice how short little pulses can come anywhere with respect to the clock edge:<\/p>\n
\r\n`timescale 1ns\/1ns\r\nmodule edge_detect_test;\r\n\r\n  reg clk = 0;\r\n  always #10 clk = ~clk;\r\n\r\n  reg btnl = 0;\r\n\r\n  wire btnl_rise;\r\n\r\n  edge_detect edge_detect(clk,btnl,btnl_rise);\r\n\r\n  initial\r\n    begin\r\n      $dumpvars(0);\r\n      \r\n      @(posedge clk)\r\n\tbtnl <= 1;\r\n      repeat (10) @(posedge clk);\r\n      btnl <= 0;\r\n      repeat (4) @(posedge clk);\r\n      #10 btnl <= 1;\r\n      #1 btnl <= 0;\r\n      repeat (4) @(posedge clk);\r\n      #19 btnl <= 1;\r\n      #1 btnl <= 0;\r\n      repeat (4) @(posedge clk);\r\n      #20 btnl <= 1;\r\n      #1 btnl <= 0;\r\n      repeat (4) @(posedge clk);\r\n      $finish;\r\n    end\r\nendmodule\r\n<\/code><\/pre>\n
The long pulse case<\/h2>\n
In the case of a long pulse, the design works just like it would\u00a0without the asynchronous set flip-flop. Here’s a timing diagram:<\/p>\n