Welcome to my little blog. I have been busy lately with working on the next generation of NMR spectrometers at Agilent. But since Agilent has decided to exit that business I have found myself with some more time to pursue my own interests. Hopefully some of those things will find their way onto my blog.
Just love the tutorials. I am taking an fpga course at UCSD extension that is making use of the Xilinx Vivado and SDK tools on the Digilent Zybo demo board. As an older RF analog EE I am finding I could benefit by expanding my skill set. Thanks again for the blog!
I’m glad to hear that the tutorials are helpful. Be sure to comment on each one if you find things confusing or especially useful. I’m still trying to get the right balance offering enough support to figure things out for yourself but not so much that you end up going through steps you don’t really understand.
im working on axi4 stream,, i am written a code for AXI-stream and i able to get one once the data ,,i feel the handshake of TVALID and TREADY is not done,, please send any referece desigin for me to check the signals in VHDL or verilog
thanks & regards
If you follow the later tutorials you will find a reference design for an AXI streaming device.
Hello Pete Johnson,
Is High-Level Synthesis (C to Silicon) going to be dominated in next few years?
Please give me your opinion!
Thank you sir!
The folks that sell C synthesis tools have been doing so for at least 20 years. With a promise that it is just around the corner. That said, I think there is a place for behavioral synthesis in FPGA and ASIC design. For datapath and signal processing the tools are pretty compelling. But they are really competing at this point with the model based design tools like Simulink. I think there really will always be a place for RTL design and it is something that all good FPGA designers should know. I think as time progresses we may use the high level tools more and more, but for the foreseeable future you need to know RTL as well.
Thanks for making these tutorials. I am new to FPGA and am mostly self-learned. I really appreciate people like you to make these materials.
very usefully tutorials, Could you make a post about how to run linux application(.elf) on qemu Petalinux?