# Tutorial 5: The Other Digit

In this tutorial, we’re going to drive the second digit of the PmodSSD display. To do this, we have to switch the cathode signal ssdcat at a rate around 500Hz. While this is taking place, we’ll also switch between switch[3:0] and switch[7:4].

# Counting to 1ms

The input clk runs at 100MHz. If we make a counter that counts 100,000 cycles, we can generate a pulse when the counter is at a particular value. We do this using a reg and an always block like this:

``````integer count = 0;
reg ms_pulse = 0;
always @(posedge clk)
if (count == 99999)
begin
count <= 0;
ms_pulse <= 1;
end
else
begin
count <= count+1;
ms_pulse <= 0;
end``````

This will give us a pulse one clock period in length every millisecond. From this, we can make our ssdcat signal:

``````always @(posedge clk)
if (ms_pulse) ssdcat <= ~ssdcat;``````

Of course, we’ll also need to initialize ssdcat to zero too:

``initial ssdcat = 0;``

When you run this design, you should see both digits light up, although not quite as bright as before. However, the digits will be the same, since we’re driving the ssd output with the value from switch[3:0] only.

# Making the Digits Different

We’re ping-ponging back and forth between the two digits now. We need to do the same thing with the input to our case statement. To do that, we declare a 4-bit input to the case statement called digit.

``wire [3:0] digit;``

Then we set the digit value to the appropriate switch bits. We’ll use an assignment statement and a conditional operator.

``assign digit = ssdcat ? switch[3:0] : switch[7:4];``

Note that the declaration of the digit signal must come before you can use it in the case statement, and before you make an assignment. Try your design out and verify that it’s possible to make two independent digits.

# Fixing the Bug

Did you notice that we have a bug? The least significant bits on the switches control the left digit. They need to be switched around so that they control the right digit. There are a couple of simple solutions for this problem. I’m going to show you the first one. Can you find the other?

Change the assignment to the digit value by switching around the conditional operator like this:

``assign digit = ssdcat ? switch[7:4] : switch[3:0];``

Now everything looks better. In the next tutorial, we’ll make a counter for counting out seconds.

Here’s a link to my version of the Verilog code for this tutorial: top.v.

## 5 thoughts on “Tutorial 5: The Other Digit”

1. As you suspected, I believe that the digits are reversed in your top.v file at the end of the tutorial.

2. Pingback: Lab5. The Other Digit – tranminhhai

3. Hi,
first off great tutorials, thanks.
In the beginning you say that we need to switch ssdcat at 500kHz.
The clk is 100MHz, so we count 10000 cycles to get 1ms, ok. And then at 1ms we switch ssdcat, but this means switching it at only 1 kHz. Shouldn’t it be 0.02ms (that gives 500 kHz), that is counting only 50 cycles of the 100 MHz clock?

4. I made a mistake in my calculation, I meant 0.002ms (that gives 500 kHz), that is counting only 200 cycles of the 100 MHz

5. Sorry for the late response. I think the text is in error. We want to switch ssdcat at 500Hz, not 500kHz. Thanks for finding the issue.

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