Vpp – Verilog Pre-Processor library


//@ use Vpp;



Vpp is a library meant for use with the vpp.pl preprocessor. The library defines useful routines for use with vpp.pl and also defines some variable corresponding to Verilog predefined tasks so that calls to the tasks do not need to be escaped. For example, since $display looks like a variable reference to the preprocessor, Vpp defines a variable called display whose value is $display. Thus you can say $display in your code and that will appear in the output text.

In addition, vpp.pl will expand `ifdef statements. This is often not desired, so Vpp defines $ifdef, $else, and $endif variables. The value of these variables is `ifdef, `else, and `endif respectively. These variables may be used to quote the ifdef constructs and prevent expansion by vpp.pl.



Returns the cieling of the log base 2 of val.

Here is an example:

 //@ my $width = 20;
 //@ my $log_width = Vpp::log2($width);
 parameter width = $width;
 parameter log_width = $log_width;

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  1. Pingback: A Verilog Preprocessor | Beyond Circuits

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